{"id":206,"date":"2020-10-26T22:52:49","date_gmt":"2020-10-26T13:52:49","guid":{"rendered":"https:\/\/withfpga.com\/?p=206"},"modified":"2020-10-26T22:52:53","modified_gmt":"2020-10-26T13:52:53","slug":"xilinx-alveo-%e3%82%b7%e3%83%aa%e3%83%bc%e3%82%ba%e3%81%ab%e3%81%a4%e3%81%84%e3%81%a6%e3%81%96%e3%81%a3%e3%81%8f%e3%82%8a%e3%81%be%e3%81%a8%e3%82%81%e3%81%a6%e3%81%bf%e3%81%9f","status":"publish","type":"post","link":"https:\/\/withfpga.com\/?p=206","title":{"rendered":"Xilinx Alveo \u30b7\u30ea\u30fc\u30ba\u306b\u3064\u3044\u3066\u3056\u3063\u304f\u308a\u307e\u3068\u3081\u3066\u307f\u305f"},"content":{"rendered":"\n<p>Xilinx \u304c\u8ca9\u58f2\u3057\u3066\u3044\u308bFPGA \u30dc\u30fc\u30c9Alveo \u30b7\u30ea\u30fc\u30ba\u306b\u3064\u3044\u3066\u30012020\u5e7410\u6708\u73fe\u5728\u306e\u60c5\u5831\u306b\u57fa\u3065\u304d\u7279\u5fb4\u3084\u4fa1\u683c\u3092\u307e\u3068\u3081\u3066\u3044\u307e\u3059\u3002<\/p>\n\n\n\n<!-- START MoshimoAffiliateEasyLink -->\n<script type=\"text\/javascript\">\n(function(b,c,f,g,a,d,e){b.MoshimoAffiliateObject=a;\nb[a]=b[a]||function(){arguments.currentScript=c.currentScript\n||c.scripts[c.scripts.length-2];(b[a].q=b[a].q||[]).push(arguments)};\nc.getElementById(a)||(d=c.createElement(f),d.src=g,\nd.id=a,e=c.getElementsByTagName(\"body\")[0],e.appendChild(d))})\n(window,document,\"script\",\"\/\/dn.msmstatic.com\/site\/cardlink\/bundle.js\",\"msmaflink\");\nmsmaflink({\"n\":\"\u9ad8\u901fEthernet \u00d7 FPGA  (FPGA\u30de\u30ac\u30b8\u30f3 No.3)\",\"b\":\"\",\"t\":\"\",\"d\":\"https:\\\/\\\/m.media-amazon.com\",\"c_p\":\"\",\"p\":[\"\\\/images\\\/I\\\/61eDrFOcfsL.jpg\"],\"u\":{\"u\":\"https:\\\/\\\/www.amazon.co.jp\\\/dp\\\/478984613X\",\"t\":\"amazon\",\"r_v\":\"\"},\"aid\":{\"amazon\":\"1781145\",\"rakuten\":\"1781140\",\"yahoo\":\"1781147\"},\"eid\":\"NJ8Yw\",\"s\":\"s\"});\n<\/script>\n<div id=\"msmaflink-NJ8Yw\">\u30ea\u30f3\u30af<\/div>\n<!-- MoshimoAffiliateEasyLink END -->\n\n\n\n<h2>Xilinx Alveo \u30b7\u30ea\u30fc\u30ba\u3068\u306f<\/h2>\n\n\n\n<p>Xilinx \u304c\u5c55\u958b\u3059\u308b\u30c7\u30fc\u30bf\u30bb\u30f3\u30bf\u30fc\u5411\u3051\u306eFPGA \u30dc\u30fc\u30c9\u306e\u3053\u3068\u3002FPGA \u5358\u4f53\u3067\u306f\u306a\u304fPCI Express \u30dc\u30fc\u30c9\u3068\u3044\u3046\u5f62\u3067\u8ca9\u58f2\u3055\u308c\u3066\u3044\u3066\u3001\u57fa\u677f\u8a2d\u8a08\u3084\u5b9f\u88c5\u3068\u3044\u3063\u305f\u9762\u5012\u306a\u3053\u3068\u3092\u8003\u3048\u308b\u3053\u3068\u306a\u304f\u8cb7\u3063\u3066\u304d\u3066\u305d\u306e\u307e\u307ePC \u306b\u633f\u305b\u3070\u4f7f\u7528\u53ef\u80fd\u3002Intel \u306ePac \u30b7\u30ea\u30fc\u30ba\u3068\u540c\u69d8\u306e\u601d\u60f3\u3067\u3042\u308b\u3002<\/p>\n\n\n\n<p>Xilinx \u306f\u30c7\u30fc\u30bf\u30bb\u30f3\u30bf\u30fc\u3067\u5927\u91cf\u306b\u4f7f\u7528\u3057\u3066\u3082\u3089\u3046\u3053\u3068\u3092\u60f3\u5b9a\u3057\u3066\u3044\u308b\u3088\u3046\u3060\u304c\u3001\u642d\u8f09\u3055\u308c\u3066\u3044\u308b\u30c1\u30c3\u30d7\u306e\u5024\u6bb5\u3068\u6bd4\u8f03\u3059\u308b\u3068\u30dc\u30fc\u30c9\u304c\u4fa1\u683c\u304c\u304b\u306a\u308a\u5b89\u3044\u306e\u3067\u3001\u7814\u7a76\u958b\u767a\u7528\u9014\u306b\u3082\u7d50\u69cb\u5229\u7528\u3055\u308c\u3066\u3044\u308b\u3089\u3057\u3044\u3002\u5f8c\u8ff0\u3059\u308bAlveo U50 \u306a\u3093\u304b\u306f\u500b\u4eba\u3067\u3082\u306a\u3093\u3068\u304b\u624b\u306e\u5c4a\u304f\u30ec\u30d9\u30eb\u3060\u3068\u601d\u3046\u3002<\/p>\n\n\n\n<p>\u4ee5\u4e0b\u3001\u500b\u4eba\u7684\u306a\u611f\u60f3\u3092\u591a\u5206\u306b\u542b\u307f\u306a\u304c\u3089\u305d\u308c\u305e\u308c\u3092\u7d39\u4ecb\u3059\u308b\u3002\u8a73\u7d30\u306a\u6bd4\u8f03\u306fXilinx \u306e\u30da\u30fc\u30b8\u3067\u884c\u306a\u3063\u3066\u307b\u3057\u3044\u3002<\/p>\n\n\n\n<p><a href=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo.html\" target=\"_blank\" rel=\"noreferrer noopener\">Xilinx Alveo<\/a><\/p>\n\n\n\n<h2>Alveo U200<\/h2>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img loading=\"lazy\" width=\"900\" height=\"740\" src=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p.jpg\" alt=\"\" class=\"wp-image-204\" srcset=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p.jpg 900w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p-300x247.jpg 300w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p-768x631.jpg 768w\" sizes=\"(max-width: 900px) 100vw, 900px\" \/><figcaption><a href=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u200.html\" target=\"_blank\" rel=\"noreferrer noopener\" title=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u200.html\">https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u200.html<\/a><\/figcaption><\/figure><\/div>\n\n\n\n<ul><li>\u304a\u305d\u3089\u304f\u3001\u6700\u3082\u30d9\u30fc\u30b7\u30c3\u30af\u306aAlveo \u30dc\u30fc\u30c9<br><ul><li>FPGA \u306fVirtex UltraScale+ VU9P \u76f8\u5f53\u306e\u3082\u306e\u3092\u642d\u8f09<\/li><\/ul><\/li><li>\u30d5\u30a1\u30f3\u306a\u3057\u306e\u30d1\u30c3\u30b7\u30d6\u30bf\u30a4\u30d7\u3068\u30d5\u30a1\u30f3\u3042\u308a\u306e\u30a2\u30af\u30c6\u30a3\u30d6\u30bf\u30a4\u30d7\u304c\u5b58\u5728\u3059\u308b\u306e\u3067\u3001\u4f7f\u7528\u74b0\u5883\u306b\u5fdc\u3058\u3066\u9078\u629e\u3059\u308b\u5fc5\u8981\u304c\u3042\u308b<\/li><li>PCIe Gen3 x16 \u3067\u7247\u65b9\u5411\u6700\u5927128 GT\/s \u306e\u8ee2\u9001\u306b\u5bfe\u5fdc<\/li><li>DDR4 Memory \u309216 GB x4 \u642d\u8f09\u3057FPGA \u304b\u3089\u30a2\u30af\u30bb\u30b9\u53ef\u80fd<\/li><li>QSFP28 \u30dd\u30fc\u30c8\u30822\u3064\u3042\u308a\u3001100 GbE \u306b\u5bfe\u5fdc<\/li><li>\u4fa1\u683c\u306fDigiKey \u306755\u4e07\u5186\u304f\u3089\u3044<br><ul><li><a href=\"https:\/\/www.digikey.jp\/product-detail\/ja\/xilinx-inc\/A-U200-P64G-PQ-G\/122-2250-ND\/9645681\" target=\"_blank\" rel=\"noreferrer noopener\" class=\"broken_link\"> A-U200-P64G-PQ-G Xilinx Inc. | \u30b3\u30f3\u30d4\u30e5\u30fc\u30bf\u6a5f\u5668 | DigiKey <\/a><br><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2>Alveo U250<\/h2>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" width=\"900\" height=\"740\" src=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p.jpg\" alt=\"\" class=\"wp-image-204\" srcset=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p.jpg 900w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p-300x247.jpg 300w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/u200-hero-p-768x631.jpg 768w\" sizes=\"(max-width: 900px) 100vw, 900px\" \/><figcaption><a href=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u250.html\" target=\"_blank\" rel=\"noreferrer noopener\" title=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u250.html\">https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u250.html<\/a><\/figcaption><\/figure>\n\n\n\n<ul><li>U200 \u306e\u5b8c\u5168\u4e0a\u4f4d\u4e92\u63db\u3002\u4e88\u7b97\u304c\u6f64\u6ca2\u306b\u3042\u308b\u306a\u3089\u3070\u3001\u3068\u308a\u3042\u3048\u305a\u3053\u3061\u3089\u3092\u9078\u3093\u3067\u304a\u3051\u3070\u554f\u984c\u306a\u3057<br><ul><li>FPGA \u306fVirtex UltraScale+ VU13P \u76f8\u5f53\u306e\u3082\u306e\u3092\u642d\u8f09<\/li><\/ul><\/li><li>Alveo U200 \u540c\u69d8\u30d1\u30c3\u30b7\u30d6\u30bf\u30a4\u30d7\u3068\u30a2\u30af\u30c6\u30a3\u30d6\u30bf\u30a4\u30d7\u304c\u5b58\u5728\u3059\u308b\u306e\u3067\u6ce8\u610f<\/li><li>PCIe, DDR4, QSFP \u306e\u4ed5\u69d8\u3082\u540c\u69d8<\/li><li>\u4fa1\u683c\u306fDigiKey \u306785\u4e07\u5186\u304f\u3089\u3044<br><ul><li><a href=\"https:\/\/www.digikey.jp\/product-detail\/ja\/xilinx-inc\/A-U250-P64G-PQ-G\/122-2252-ND\/9645683\" target=\"_blank\" rel=\"noreferrer noopener\" class=\"broken_link\"> A-U250-P64G-PQ-G Xilinx Inc. | \u30b3\u30f3\u30d4\u30e5\u30fc\u30bf\u6a5f\u5668 | DigiKey <\/a><br><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2>Alveo U280<\/h2>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img loading=\"lazy\" width=\"2560\" height=\"1707\" src=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-scaled.jpg\" alt=\"\" class=\"wp-image-205\" srcset=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-scaled.jpg 2560w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-300x200.jpg 300w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-1024x683.jpg 1024w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-768x512.jpg 768w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-1536x1024.jpg 1536w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/280-passive-hero-2048x1365.jpg 2048w\" sizes=\"(max-width: 2560px) 100vw, 2560px\" \/><figcaption><a href=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u280.html\" target=\"_blank\" rel=\"noreferrer noopener\" title=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u280.html\">https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u280.html<\/a><\/figcaption><\/figure><\/div>\n\n\n\n<ul><li>U200, U250 \u3068\u306f\u9055\u3044\u3001HBM2 \u3092\u642d\u8f09\u3057\u305f\u3053\u3068\u3092\u58f2\u308a\u306b\u3057\u305f\u30ab\u30fc\u30c9<br><ul><li>FPGA \u306fVirtex UltraScale+ VU37P \u76f8\u5f53\u306e\u3082\u306e\u3092\u642d\u8f09<\/li><\/ul><\/li><li>HBM2 \u306fDDR4 \u3088\u308a\u3082\u5727\u5012\u7684\u306a\u5e83\u5e2f\u57df\u3067\u306e\u30e1\u30e2\u30ea\u30a2\u30af\u30bb\u30b9\u304c\u53ef\u80fd<br><ul><li>HBM2 \u306e\u5bb9\u91cf\u81ea\u4f53\u306f8 GB \u7a0b\u5ea6\u306b\u3068\u3069\u307e\u308b<\/li><\/ul><\/li><li>DDR4 \u3082\u642d\u8f09\u3057\u3066\u3044\u308b\u304c\u3001\u5bb9\u91cf\u306f 32 GB<\/li><li>PCIe Gen3 x16 \u3068Gen4 x8 \u306b\u5bfe\u5fdc<\/li><li>QSFP \u306e\u4ed5\u69d8\u306fU200, U250 \u3068\u540c\u69d8<\/li><li>\u30d1\u30c3\u30b7\u30d6\u30bf\u30a4\u30d7\u3068\u30a2\u30af\u30c6\u30a3\u30d6\u30bf\u30a4\u30d7\u304c\u5b58\u5728<\/li><li>\u4fa1\u683c\u306fDigiKey \u306784\u4e07\u5186\u304f\u3089\u3044<br><ul><li><a href=\"https:\/\/www.digikey.jp\/product-detail\/ja\/xilinx-inc\/A-U280-P32G-PQ-G\/122-2277-ND\/10274213\" target=\"_blank\" rel=\"noreferrer noopener\" class=\"broken_link\"> A-U280-P32G-PQ-G Xilinx Inc. | \u30b3\u30f3\u30d4\u30e5\u30fc\u30bf\u6a5f\u5668 | DigiKey <\/a><br><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2>Alveo U50<\/h2>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img loading=\"lazy\" width=\"4679\" height=\"4000\" src=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket.png\" alt=\"\" class=\"wp-image-202\" srcset=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket.png 4679w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket-300x256.png 300w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket-1024x875.png 1024w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket-768x657.png 768w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket-1536x1313.png 1536w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket-2048x1751.png 2048w\" sizes=\"(max-width: 4679px) 100vw, 4679px\" \/><figcaption><a href=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u50.html\" target=\"_blank\" rel=\"noreferrer noopener\" title=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u50.html\">https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u50.html<\/a><\/figcaption><\/figure><\/div>\n\n\n\n<ul><li>\u6700\u5b89\u5024\u306eAlveo \u3067\u3001\u500b\u4eba\u3067\u8cfc\u5165\u3059\u308b\u306a\u3089\u3053\u3061\u3089\u304c\u30d5\u30a1\u30fc\u30b9\u30c8\u30c1\u30e7\u30a4\u30b9<br><ul><li>FPGA \u306fVirtex UltraScale+ VU35P \u76f8\u5f53\u306e\u3082\u306e\u3092\u642d\u8f09<\/li><\/ul><\/li><li>U280 \u540c\u69d8HBM2 \u30928 GB \u642d\u8f09<\/li><li>DDR4 \u306e\u642d\u8f09\u306f\u306a\u3057<\/li><li>PCIe Gen3 x16 \u3068Gen4 x8 x2 \u306b\u5bfe\u5fdc<\/li><li>QSFP28 \u306f1\u30dd\u30fc\u30c8\u306e\u307f\u306e\u642d\u8f09<\/li><li>\u30d5\u30a1\u30f3\u306a\u3057\u306e\u30d1\u30c3\u30b7\u30d6\u30bf\u30a4\u30d7\u306e\u307f\u306a\u306e\u3067\u51b7\u5374\u306b\u6ce8\u610f<\/li><li>\u4fa1\u683c\u306fDigiKey \u306733\u4e07\u5186\u304f\u3089\u3044\u3067\u3001\u500b\u4eba\u3067\u3082\u306a\u3093\u3068\u304b\u624b\u304c\u5c4a\u304f\u30ec\u30d9\u30eb<br><ul><li><a href=\"https:\/\/www.digikey.jp\/product-detail\/ja\/xilinx-inc\/A-U50-P00G-PQ-G\/122-A-U50-P00G-PQ-G-ND\/10488835\" target=\"_blank\" rel=\"noreferrer noopener\" class=\"broken_link\">A-U50-P00G-PQ-G Xilinx Inc. | \u30b3\u30f3\u30d4\u30e5\u30fc\u30bf\u6a5f\u5668 | DigiKey<\/a><br><\/li><\/ul><\/li><\/ul>\n\n\n\n<h2>Alveo U25<\/h2>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><img loading=\"lazy\" width=\"700\" height=\"500\" src=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/alveo-u25-hero-of-card.jpg\" alt=\"\" class=\"wp-image-203\" srcset=\"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/alveo-u25-hero-of-card.jpg 700w, https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/alveo-u25-hero-of-card-300x214.jpg 300w\" sizes=\"(max-width: 700px) 100vw, 700px\" \/><figcaption><a href=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u25.html\" target=\"_blank\" rel=\"noreferrer noopener\" title=\"https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u25.html\">https:\/\/japan.xilinx.com\/products\/boards-and-kits\/alveo\/u25.html<\/a><\/figcaption><\/figure><\/div>\n\n\n\n<ul><li>\u6700\u8fd1\u8ffd\u52a0\u3055\u308c\u305f\u30dc\u30fc\u30c9\u3067\u3001Smart NIC \u3068\u3057\u3066\u5229\u7528\u3059\u308b\u3053\u3068\u3092\u524d\u63d0\u3068\u3057\u3066\u3044\u308b(\u3089\u3057\u3044)<br><ul>\n\t\t\t<li>FPGA \u306f(\u304a\u305d\u3089\u304f) Zynq UltraScale+ MPSoC ZU19EG \u76f8\u5f53\u306e\u3082\u306e\u3092\u642d\u8f09<\/li>\n\t\t\t<li>Zynq \u306a\u306e\u3067FPGA \u3060\u3051\u3067\u306a\u304fCPU \u3082\u540c\u4e00\u30c1\u30c3\u30d7\u306b\u642d\u8f09\u3055\u308c\u3066\u3044\u308b\u306e\u304c\u7279\u5fb4<\/li>\n\t\t<\/ul><\/li><li>DDR4 \u306f2 GB \u30684 GB \u30921 \u679a\u305a\u3064\u642d\u8f09<\/li><li>PCIe Gen3 x8 x2 \u306b\u5bfe\u5fdc<\/li><li>SFP 28 \u30922\u30dd\u30fc\u30c8\u642d\u8f09\u3057\u300125 GbE \u306b\u5bfe\u5fdc<\/li><li>(\u304a\u305d\u3089\u304f)\u30d5\u30a1\u30f3\u306a\u3057\u306e\u30d1\u30c3\u30b7\u30d6\u30bf\u30a4\u30d7\u306e\u307f<\/li><li>\u4fa1\u683c\u306f\u78ba\u8a8d\u3067\u304d\u305a\u3002\u307e\u3060\u5341\u5206\u306b\u51fa\u8377\u3055\u308c\u3066\u306a\u3044\uff1f<\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Xilinx \u304c\u8ca9\u58f2\u3057\u3066\u3044\u308bFPGA \u30dc\u30fc\u30c9Alveo \u30b7\u30ea\u30fc\u30ba\u306b\u3064\u3044\u3066\u30012020\u5e7410\u6708\u73fe\u5728\u306e\u60c5\u5831\u306b\u57fa\u3065\u304d\u7279\u5fb4\u3084\u4fa1\u683c\u3092\u307e\u3068\u3081\u3066\u3044\u307e\u3059\u3002 \u30ea\u30f3\u30af Xilinx Alveo \u30b7\u30ea\u30fc\u30ba\u3068\u306f Xilinx \u304c\u5c55\u958b\u3059\u308b\u30c7\u30fc\u30bf\u30bb\u30f3&#8230;<\/p>\n","protected":false},"author":1,"featured_media":202,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spay_email":""},"categories":[2],"tags":[18,19,23,20,21,22,17],"jetpack_featured_media_url":"https:\/\/withfpga.com\/wp-content\/uploads\/2020\/10\/U50_Hero_1_Bracket.png","_links":{"self":[{"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/posts\/206"}],"collection":[{"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/withfpga.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=206"}],"version-history":[{"count":6,"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/posts\/206\/revisions"}],"predecessor-version":[{"id":212,"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/posts\/206\/revisions\/212"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/withfpga.com\/index.php?rest_route=\/wp\/v2\/media\/202"}],"wp:attachment":[{"href":"https:\/\/withfpga.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=206"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/withfpga.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=206"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/withfpga.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=206"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}